Also known as: jeffrdinerware
ASICFPGA Design Engineer with a proven ability to work and thrive both independently and in a team environment, prioritizing multiple projects and meeting deadlines. Functions well in a team environment communicating effectively with all levels of an organization. Eleven years of ASICFPGA design flow experience with demonstrated technical expertise in the following areas Data compression and encryption Verilog and VHDL for RTL or behavioral modeling Logic synthesis using Synopsys Design Compiler, Synplicity Synplify Pro, and Xilinx ISEXST Studied Magma synthesis and layout for RTL to GDSII flow. RTLGate level simulation using Synopsys VCS, debug using Novas VerdiDebussy DFT methodology ATPG using Synopsys TetraMAX JTAG insertion using Synopsys BSD Compiler Formal Verification with Logic Equivalency checking using Verplex LEC TclTk scripting language C for embedded applications and utility applications Specialties RTL designimplementation, synthesis, and verification.
