ASICFPGA Design Engineer with a proven ability to work and thrive both independently and in a team environment, prioritizing multiple projects and meeting deadlines. Functions well in a team environment communicating effectively with all levels of an organization. Eleven years of ASICFPGA design flow experience with demonstrated technical expertise in the following areas Data compression and encryption Verilog and VHDL for RTL or behavioral modeling Logic synthesis using Synopsys Design Compiler, Synplicity Synplify Pro, and Xilinx ISEXST Studied Magma synthesis and layout for RTL to GDSII flow. RTLGate level simulation using Synopsys VCS, debug using Novas VerdiDebussy DFT methodology ATPG using Synopsys TetraMAX JTAG insertion using Synopsys BSD Compiler Formal Verification with Logic Equivalency checking using Verplex LEC TclTk scripting language C for embedded applications and utility applications Specialties RTL designimplementation, synthesis, and verification.read more ...read less ...
University Of Colorado At Denver
Engineer
Principal Ic Design At Broadcom
Senior Asic Design Engineer At Marvell Semiconductor
Disclaimer: PeekYou is not a consumer reporting agency per the Fair Credit Reporting Act. You may not use our site or service, or the information provided, to make decisions about employment, admission, consumer credit, insurance, tenant screening or any other purpose that would require FCRA compliance. For more information governing use of our site, please review our Terms of Service.
Copyright 2024 PeekYou.com. A Patent Pending People Search Process. All Rights Reserved.
By continuing to use our site, you consent to the placement of cookies on your browser and agree to the terms of our Privacy Policy. More details