143 Matches for Peter Orlando

Peter Orlando Age 59

Grafton, MA

Peter Orlando lives in Grafton, MA.

Peter Orlando

New York, NY

Also known as: allpeterdout

Views are my own

Peter Orlando

New York, NY

Also known as: Peetaahbread

Peter Orlando lives in New York, NY.

Peter S. Orlando

Boulder, CO

**Goal Provide technical leadership in DFT for VLSI SoC designs while meeting customer Test Coverage & DPPM goals on high volume production chips. **Technical Merits A proven strategist in implementing DFT for hierarchical or flat designs. Provide DFT structures for embedded IP (PLL, DLL and other IP) and high speed I/F. Also provides accessibility through JTAG for silicon debug during production. Verification of DFT structures: ATPG pattern simulation of stuck-at, transition (PLL Control), Small Delay Defect, Path Delay and IDDQ models. Memory BIST simulation with memory repair. Parametric testing of SoC IO through boundary scan scan. **Communication Good communication skills to facilitate technical collaboration with customers, colleagues, internal and external IP providers and vendors to provide process improvements and solve complex design problems. Specialties - Knowledgeable of the VLSI design process from RTL to GDS - DFT specification and implementation at IP or SoC levels - Usage of JTAG I/F - RTL Implementation for DFT structures - SoC Synthesis(dc_shell) - Simulation and validation of DFT structures (ncsim, vcs) - Scan insertion(DFT Compiler) - Memory BIST Insertion(Logic Vision and Atrenta SpyGlass) - ATPG pattern generation (Tetramax) - Writing timing constraints for DFT(STA) - Formal verification at RTL and Gate post DFT insertion(Formality)

• #North Carolina State University