Extensive background in verification and test of numerous ASIC, SoC and CPU designs. Verification efforts have included testplan definition, testbench development, random stimulus generation, coverage completion and simulation debug. Have effectively used C, C++, Perl, Verilog, SystemVerilog and other languages on verification assignments. A strong programmer with a keen eye for improving methodologies while taking best advantage of existing tools. A great communicator and collaborator. Specialties Verification automation and methodology improvement, Random stimulus generation, Functional coverage implementation and completion, Reference model (C/C++) development, Simulation debug.read more ...read less ...
The University Of Texas At Austin
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